In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities there has been, and continues to be, efforts toward scaling down the device dimensions on semiconductor wafers. In order to accomplish such a high device packing density, smaller feature sizes are required. This may include the width and spacing of interconnecting lines and the surface geometry such as the corners and edges of various features.
The requirement of small features with close spacing between adjacent features requires high resolution photolithographic processes. In general, lithography refers to processes for pattern transfer between various media. It is a technique used for integrated circuit fabrication in which, for example, a silicon wafer is coated uniformly with a radiation-sensitive film (e.g., a photoresist), and an exposing source (such as ultraviolet light, x-rays, or an electron beam) illuminates selected areas of the film surface through an intervening master template (e.g., a mask or reticle) to generate a particular pattern. The exposed pattern on the photoresist film is then developed with a solvent called a developer which makes the exposed pattern either soluble or insoluble depending on the type of photoresist (i.e., positive or negative resist). The soluble portions of the resist are then removed, thus leaving a photoresist mask corresponding to the desired pattern on the silicon wafer for further processing.
Clearly, projection lithography is a powerful and important tool for integrated circuit processing. In order to further increase the packing density of integrated circuits, however, not only is the quality of lithographic imaging important, but the accuracy with which an image can be positioned on the surface of a substrate is also of considerable importance. Because integrated circuits are fabricated by patterning a plurality of layers in a particular sequence to generate features that require a particular spatial relationship with respect to one another, each layer must be properly aligned with respect to previously patterned layers to minimize the size of individual devices and thus maximize the packing density on the substrate. Presently, having a perfect overlap (i.e., zero registration error) is not easily achievable. Consequently, a registration or overlay tolerance is required between two layers to ensure reliability in the construction of the resulting device. This registration or overlay tolerance undesirably increases the size of various structures and therefore attempts are made to minimize the tolerance.
As is evident from the discussion above, it is desirable to minimize the registration tolerance needed to form overlying patterns in order to improve the packing density of structures which form the integrated circuit. One solution which has been used to maximize the pattern overlay accuracy of various layers is to form one or more alignment marks or patterns on the underlying substrate and each mask. When the alignment marks or patterns on the substrate and mask are optically aligned, for example, then the remainder of the circuit patterns are assumed to be aligned.
Another type of alignment system uses an alignment mark scheme as illustrated in prior art FIG. 1, which illustrates a fragmentary cross section of a substrate such as a silicon wafer. A substrate 50 has one or more recesses 52 formed therein which serve as alignment marks. Each recess preferably has a depth 54 which is a function of the alignment radiation wavelength (e.g., a depth of .lambda./4). The predetermined depth 54 provides a destructive interference phenomena upon the reflection off the marks 52 which allows the alignment marks 52 to be more effectively "seen" (i.e., they exhibit a better reflective contrast than the neighboring non-recessed regions and are thus more visible).
An exemplary prior art alignment system 58 uses the alignment marks 52 of prior art FIG. 1 in the following manner, as illustrated in prior art FIG. 2. An alignment light source (not shown) illuminates a grating of alignment marks 52 with radiation 60 which has its diffracted orders reflect off the alignment marks 52 and get captured by a lens 62 and directed toward a mask 64. The reflected radiation 60 is used as a signal to detect the alignment between the mask 64 and the substrate 50.
As will become apparent in the discussion that follows, the prior art alignment mark structure suffers from some disadvantages which prevents alignment accuracy from being maximized. There is thus a need in the art for improved alignment structures and systems as well as efficient manufacturing methods for their implementation.